1. Field of the Invention
The present invention relates generally to oscillators, and more particularly to a variable-frequency, digitally controlled ring oscillator with adjustable delay.
2. Description of the Related Art
There are numerous integrated circuit (IC) applications where, for proper operation, it is necessary to provide precise timing or synchronization of one portion of a circuit with another. Such timing is generally provided by a local oscillator whose frequency is sufficiently accurate for the requirements of the circuit being timed or synchronized. Depending on the degree of accuracy required, an oscillator may be very simple and inexpensive where frequency range can have a wide range, or relatively complex and expensive where accuracy (less than a few percent error) in frequency is required. It is desirable to have an oscillator which is both simple and inexpensive, and yet operates at an accurate frequency.
Complementary metal oxide semiconductor (CMOS) manufacturing technology is highly developed, and for many applications, is the technology of choice in designing and implementing large scale integrated circuits. Various kinds of oscillators have been used for on-board timing of other circuitry on CMOS integrated circuits. One kind of oscillator readily used by CMOS technology is a ring oscillator. In this kind of oscillator, there are no inductor-capacitor tuned circuits, which in other oscillators are used to accurately set the frequency of operation. Instead of tuned circuits, a ring oscillator has an odd number of identical and very simple inverting stages connected in series, with an output of each stage coupled to an input of the next stage and with the output of the last stage coupled to the input of the first stage. In one embodiment, each stage is an inverter having a pair of serially connected CMOS transistors whose output switches to a high level, a xe2x80x9c1xe2x80x9d, when a low level, a xe2x80x9c0xe2x80x9d is applied to the input thereof and switches to a xe2x80x9c0xe2x80x9d when a xe2x80x9c1xe2x80x9d is applied to the input thereof. The frequency of operation of this type of oscillator is determined by the speed of progression of a switching event of xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, and xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d from one stage to another around the ring, and by the number of stages. A conventional CMOS ring oscillator as part of an IC chip may have its own frequency of operation within a range of frequencies. When precise timing of a circuit is required (e.g., frequency accuracy to within a few percent), delay control logic circuits are part of the ring oscillator circuit that are used to compensate for processes during manufacture, synchronizing data to be in-phase, or for a controlled fixed frequency.
One design of a ring oscillator circuit with delay compensation includes a capacitive load added at the output for adjustable delay. In such a design, the resistance of load devices is highly temperature sensitive. Variations in resistance are due primarily to changes in surface carrier mobility with temperature. When a time constant generating circuit is constructed on an integrated circuit using a resistive load device and an ordinarily constructed integrated circuit capacitor, the RC time constant varies significantly with changes in temperature. This creates great problems in stabilizing the oscillator frequency. Another problem with this type of design includes less accurate adjustment. Also, this design is typically too large to implement in CMOS circuits.
Another ring oscillator 10, shown in FIG. 1, includes a truncation logic ring control design. Multiple inverters 20 connect in multiple loops 30 that junction at a multiplexer 40. Dynamic truncation of the ring maintains a locked predetermined output signal 50 (OSC_OUT). This design is similarly disclosed in a sophisticated design in U.S. Pat. No. 6,157,267 (hereinafter xe2x80x9c267 patent xe2x80x9d), which is hereby incorporated by reference.
One problem encountered with such a design includes the nature of the truncation loops which have embedded counters (a 50% duty cycle oscillator signal cannot be generated). Since each truncation loop in the 267 patent includes a delay element, a counter, and gating logic, the minimum achievable delay for a given truncation loop is dependent on the sum of these three elements which restricts the maximum oscillator frequency obtainable for a given application.
In FIG. 1, the ring oscillator 10 uses truncation which creates large monotonic steps when varying frequency. The delay control switching logic circuit 20 generally creates different phase steps at these truncation locations 30 that is minimal (i.e., much less than 2:1). Problems inherent with this oscillator design include it being larger and typically more complex, which creates different phase steps in the multiple truncation locations 30 which are not the same.
Therefore, it is desirable to have a ring oscillator design that is relatively inexpensive, yet generates an output frequency signal that can be set to a desired level of accuracy using a logic controller and a single delay control signal that is the same to all portions of the inverter ring. The present invention provides an effective and inexpensive solution to this problem of accuracy in frequency of operation of a digital ring oscillator for implementation by CMOS technology as part of an IC chip using standard cell placement.
It is a primary object of the present invention to provide a digital variable-frequency digital ring oscillator having multiple element paths, wherein an output frequency of the oscillator has adjustable delay that can be directly controlled by a single control signal connected to each macro delay forming the inverter ring circuit.
To achieve the above object, the present invention provides a pulse circulating circuit formed by connecting inverters in a ring configured in discrete macro delay loops to generate an output signal by circulating a pulse signal, thus forming a digital oscillator. The oscillator functions so that the output frequency of the pulse circulating circuit is changed by increasing or decreasing the number of the macro delay units by an initial acquisition of a desired operational frequency by truncating the multiple element paths. An important characteristic of this macro delay unit comprises a temperature compensation section that is part of each macro delay unit circuit forming the ring of inverters. The macro delay units are serially connected as fine delay inverter units, each provide small and precise delay changes, thereby providing greater flexibility in controlling both the frequency of operation of the oscillator and the wave shape of the output signal. The digital oscillator is well suited for implementation by CMOS technology as part of an IC chip using standard cell placement. The present invention achieves very fine delay adjustments by increasing or decreasing the drive strength of inverting delay elements, thus creating a variable delay element. By using the most basic logic function as the variable delay element, the maximum oscillation frequencies for a given technical application can be realized. The present invention uses a hybrid approach of a truncation ring structure where the truncation loops are comprised of variable delay elements. This allows the truncation ring to be set as a fixed truncation loop following a coarse acquisition. The variable delay elements are then used to track the target frequency.